Aleksandar Haber on LinkedIn: RS Flip-Flop | SR Latch - Basics and Verilog FPGA Implementation in Vivado…

Flip or Flop: Back to the Basics

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(a) Provide a block diagram and a function table for the D-type flip-flop with falling edge-triggered clock and asynchronous preset and clear inputs. Both asynchronous inputs are active high.[5 marks](b) Draw a circuit diagram of a 4-bit shift register employed in the divide-by-two operation with initial conditions of 1110. Show the progression of the output.[5 marks](c) Design a finite state machine to realize a 3-bit down counter. Clearly show the steps of your design process.[10 marks]